HW/SW Co-Design of a Specific Accelerator for Robotic Computer Vision

Susana Ortega Cisneros, Miguel Ángel Carrazco Díaz, Adrian Pedroza de la Crúz, Juan José Raygoza Panduro, Jorge Rivera Domínguez, Federico Sandoval Ibarra


This paper presents an image processing application focused on robotic computer vision. The co-design is divided into three main parts: a hardware accelerator, a PCIe® based framework for HW/SW link, and application software. The implemented accelerator performs preprocessing for facial recognition in order to reduce the workload in the main system processor. The hardware layer is implemented in Altera FPGAs, while the project software layer provides a device driver for Linux to link the user application with the coprocessor. The user application controls the data transfer between the operating system and the device driver. The platform allows rapid prototyping of accelerators, taking advantage of the duality of a programmable hardware and a general purpose processor connected through a PCIe® link. The proposed architecture enables co-design of various image processing algorithms. In this case, the results of the design of an accelerator that performs histogram equalization for contrast correction of color images are presented.



Accelerator for computer vision, design automation, field-programmable gate array (FPGA), hardware accelerator, hardware design, high performance computing, Linux driver, PCIe framework, Verilog

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